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Features
* * * * * * * * * * * *
AM/FM Tuner Front End with Integrated PLL AM Up-conversion System (AM-IF: 10.7 MHz) FM Down-conversion System (FM-IF: 10.7 MHz) IF Frequencies up to 25 MHz Fine-tuning Steps: AM = 1 kHz and FM = 50 kHz/25 kHz/12.5 kHz Fast Fractional PLL (Lock Time < 1 ms) Inclusive Spurious Compensation Fast RF-AGC, Programmable in 1-dB Steps Fast IF-AGC, Programmable in 2-dB Steps Fast Frequency Change by 2 Programmable N-divider Two DACs for Automatic Tuner Alignment High S/N Ratio 3-wire Bus (Enable, Clock and Data; 3V and 5V Microcontrollers-compatible)
AM/FM Front End IC T4260
1. Description
The T4260 is an advanced AM/FM receiver with integrated fast PLL as a single-chip solution based on Atmel(R)'s high-performance BICMOS II technology. The low-impedance driver at the IF output is designed for the A/D of a digital IF. The fast tuning concept realized in this part is based on patents held by Atmel and allows lock times less than 1 ms for a jump over the FM band with a step width of 12.5 kHz. The AM up-conversion and the FM down-conversion allows an economic filter concept. An automatic tuner alignment is provided by built-in DACs for gain and offset compensation. The frequency range of the IC covers the FM broadcasting band as well as the AM band. The low current consumption helps the designers to achieve economic power consumption concepts and helps to keep the power dissipation in the tuner low.
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Figure 1-1.
Block Diagram
MXFMOB MXAMOA MXFMOA MXAMOB 43 44 39 40 IFINAM IFREF ININFM 34 35 36 IFAGCFM IFAGCA2 IFOUTA IFOUTB IFAGCA1 29 30 31 10 32 41 37 RF/IF SUPPLY 4 5 6 7 8 PLL SUPPLY AGC 15 26 28 VSPLL VRPLL GNDPLL 38 14 VST VRT GNDT VRVCO
MXFMIA MXFMIB GNDRF MXAMIB MXAMIA
RFAGCA1 RFAGCFM RFAGCA2
42 33 12 AGC
DIV BUS
23 24 25 11
EN CLK DATA SW2/AGC SW1 DAC2 DAC1
AMAGCO FMAGCO
AM 9 3
FM
13 SW-AMLF PD R DIV VCO 2 1
N DIV
22 OSCBUF
21 20 19 OSCE OSCB OSCGND
27 REFFREQ
16 FMLF
17 AMLF
18 VTUNE
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2. Pin Configuration
Figure 2-1. Pinning SSO44
DAC1 DAC2 FMAGCO MXFMIA MXFMIB GNDRF MXAMIB MXAMIA AMAGCO IFAGCA2 SW2/AGC RFAGCA2 SW1 VRVCO VSPLL FMLF AMLF VTUNE OSCGND OSCE OSCB OSCBUF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 MXFMOB MXFMOA RFAGCA1 VST MXAMOA MXAMOB GNDT VRT IFINFM IFINAM IFREF RFAGCFM IFAGCA1 IFAGCFM IFOUTA IFOUTB GNDPLL REFFREQ VRPLL DATA CLK EN
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Description
Symbol DAC1 DAC2 FMAGCO MXFMIA MXFMIB GNDRF MXAMIB MXAMIA AMAGCO IFAGCA2 SW2/AGC RFAGCA2 SW1 VRVCO VSPLL FMLF AMLF VTUNE OSCGND OSCE Function DAC1 output DAC2 output FM AGC current FM mixer input A FM mixer input B RF ground AM mixer input B AM mixer input A AM AGC current AM IF-AGC filter 2 Switch 2/AM AGC voltage RF AM-AGC filter 2 Switching output 1 VCO reference voltage PLL supply voltage FM loop filter AM loop filter Tuning voltage Oscillator ground Oscillator emitter
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Table 2-1.
Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Pin Description (Continued)
Symbol OSCB OSCBUF EN CLK DATA VRPLL REFFREQ GNDPLL IFOUTB IFOUTA IFAGCFM IFAGCA1 RFAGCFM IFREF IFINAM IFINFM VRT GNDT MXAMOB MXAMOA VST RFAGCA1 MXFMOA MXFMOB Function Oscillator base Oscillator buffer output/input 3-wire bus Enable 3-wire bus Clock 3-wire bus Data PLL reference voltage PLL reference frequency PLL ground IF output B IF output A FM IF-AGC filter AM IF-AGC filter 1 RF FM-AGC filter IF amplifier reference input IF amplifier AM input IF amplifier FM input Tuner reference voltage Tuner ground AM mixer output B AM mixer output A Tuner supply voltage RF AM-AGC filter 1 FM mixer output A FM mixer output B
3. Functional Description
The T4260 implements an AM up-conversion reception path from the RF input signal to the IF output signal. A VCO and an LO prescaler for AM are integrated to generate the LO frequency to the AM mixer. The FM reception path generates the same LO frequency from the RF input signal by a down-conversion to the IF output. The IF A/D output is designed for digital signal processing. The IF can be chosen in the range of 10 MHz to 25 MHz. Automatic gain control (AGC) circuits are implemented to control the preamplifier stages in the AM and FM reception paths. For improved performance, the PLL has an integrated special 2-bit shift fractional logic with spurious suppression that enables fast frequency changes in AM and FM mode by a low step frequency (fPDF). In addition, two programmable DACs (Digital to Analog Converter) support the alignment via a microcontroller. For a double-tuner concept, external voltage can be applied at the input of the DACs, the internal PLL can switched off and the OSC buffer (output) can also be used as input. Several register bits (bit 0 to bit 145) are used to control the circuit's operation and to adapt certain circuit parameters to the specific application. The control bits are organized in four 8-bit, four 16-bit and three 24-bit registers that can be programmed by the 3-wire bus protocol. The bus protocol and the bit-to-register mapping is described in Section 8. "3-wire Bus Description" on page 10. The meaning of the control bits is mentioned in the following sections.
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4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referred to GND Parameters Analog supply voltage, pins 15 and 41 Maximum power consumption Ambient temperature range Storage temperature range Junction temperature Symbol VST, VSPLL Ptot Tamb Tstg Tj Value 10 1.0 -40 to +85 -40 to +150 150 Unit V W C C C
5. Thermal Resistance
Parameters Junction ambient, soldered to PCB Symbol RthJA Value 52 Unit K/W
6. Operating Range
Parameters Supply voltage range , pins 15 and 41 Ambient temperature Oscillator frequency, pin 21 Note: 1. VST and VSPLL must have the same voltage.
(1)
Symbol VST, VSPLL Tamb Rfi
Min. 8 -40 60
Typ. 8.5
Max. 10 85 175
Unit V C MHz
7. Electrical Characteristics
Test conditions (unless otherwise specified): VST/VSPLL = +8.5V, Tamb = +25C No. 1 1.1 1.2 2 2.1 Parameters Power Supply Supply voltage Supply current PLL Divider Programmable R-divider Programmable (VCO) N-divider (1 kHz step frequency) Reference oscillator input voltage Reference frequency 14-bit register 2-bit x 18-bit register switchable via bit 5 f = 0.1 MHz to 3 MHz FM AM 27 3 16383 A AM and FM mode, VS = 10V 15, 41 15, 41 VS IS 8 70 8.5 85 10 110 V mA C A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
2.2
3
262143
A
2.3 2.4
100 120 120 150 2850 10000 10000
mVrms kHz kHz
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40C to +85C) but are tested at +25C
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7. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5V, Tamb = +25C No. Parameters Settling time in FM mode (switching from 87.5 MHz to 108 MHz or vice versa) AMLF/FMLF Output current 1 Output current 2 Output current 3 Output current 4 Leakage current VTUNE Saturation voltage LOW Saturation voltage HIGH DAC1, DAC2 Output current Output voltage Maximum offset range Minimum offset range Maximum gain range Minimum gain range Oscillator Frequency range Fractional frequency range Buffer output Buffer input Input voltage FM Mixer Frequency range Input IP3 Input impedance Input capacitance Noise figure Conversion transconductance F 2.6 14 3.1 3.6 75 133 3.5 4 163 MHz dBV k pF dB ms B C D D C D(1) Slave mode Fractional mode 21 21 22 22 21 VOSC 60 60 150 100 150 170 140 MHz MHz mVrms mVrms mVrms B A C C A Offset = 0, gain = 58 Offset = 127, gain = 58 Gain = 255, offset = 64 Gain = 0, offset = 64 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 IDAC1,2 VDAC1,2 0.3 0.9 -0.9 2.06 0.63 0.98 -0.98 2.09 0.67 1 VS - 0.6 1.1 -1.1 2.13 0.73 mA V V V - - D A A(1) A(1) A(1) A(1) VSATL = VTUNEMIN VSATH = VSPLL - VTUNEMAX 18 18 VSATL VSATH 100 200 400 500 mV mV C C FMLF, AMLF = 1.8V FMLF, AMLF = 1.8V FMLF, AMLF = 1.8V FMLF, AMLF = 1.8V FMLF, AMLF = 1.8V 16, 17 16, 17 16, 17 16, 17 16, 17 40 80 850 1650 50 100 1000 2000 60 120 1250 2450 10 A A A A nA A(1) A(1) A(1) A(1) A(1) Test Conditions fPD = 50 kHz IPD = 2 mA Pin Symbol Min. Typ. Max. Unit Type*
2.5
1
ms
B
3 3.1 3.2 3.3 3.4 3.5 4 4.1 4.2 5 5.1 5.2 5.3 5.4 5.5 5.6 6 6.1 6.2 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 7.6
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40C to +85C) but are tested at +25C
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7. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5V, Tamb = +25C No. 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.2 10 10.1 10.2 Parameters Frequency range Input IP3 Input impedance Noise figure Conversion transconductance Isolation Isolation AM-FM IF suppression RF-AGC Frequency range Output current Output current time constant FM AM FM AM FM rising FM falling AM symmetrical 88 dBV 89 dBV 90 dBV 91 dBV 92 dBV 93 dBV 94 dBV 10.4 RF-AGC AM threshold (programmable with bit 12 - bit 15) 95 dBV 96 dBV 97 dBV 98 dBV 99 dBV 100 dBV 101 dBV 102 dBV 103 dBV Note: 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 75 0.075 5 5 2 50 40 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 107 163 26 MHz MHz mA mA ms ms ms dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV A B 40 40 dB dB C C F 2.6 Test Conditions Pin Symbol Min. 0.075 133 2.5 10 3.1 3.6 Typ. Max. 26 Unit MHz dBV k dB mS Type* B C D C D(1) AM Mixer (Symmetrical Input)
10.3
C A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Minimum and maximum limits are characterized for entire temperature range (-40C to +85C) but are tested at +25C
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7. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5V, Tamb = +25C No. Parameters Test Conditions 91 dBV 92 dBV 93 dBV 94 dBV 95 dBV 96 dBV 97 dBV 10.5 RF-AGC FM threshold (programmable with bit 12 - bit 15) 98 dBV 99 dBV 100 dBV 101 dBV 102 dBV 103 dBV 104 dBV 105 dBV 106 dBV 11 11.1 11.2 11.3 IF Amplifier Frequency range Output voltage Distortion (2-tone IM3) Gain (programmable in 2-dB steps) Input impedance IF-AGC 109 dBV 111 dBV IF-AGC AM/FM threshold (programmable with bit 0 - bit 2) 113 dBV 115 dBV 117 dBV 118 dBV 119 dBV 121 dBV 12.2 12.3 AGC dynamic range AGC time constant (external capacity 100 nF) FM rising FM falling AM symmetrical 29/30 29/30 29/30 29/30 29/30 29/30 29/30 29/30 108 110 111 113 116 117 118 120 109 111 113 115 117 118 119 121 40 16 4 200 112 114 115 117 121 122 123 126 dBV dBV dBV dBV dBV dBV dBV dBV dB s ms ms A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) B D f1 = 10.7 MHz f2 = 10.75 MHz RL = 2 x 300 Minimum gain Maximum gain FM AM 36, 35 10 117 55 12 42 330 2500 25 MHz dBV dB dB dB A B A Pin 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 Symbol Min. 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Typ. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Max. 93 95 96 96 98 99 102 101 102 104 104 105 106 107 108 109 Unit dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV Type* A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1) A(1)
11.4 11.5 12
A D
12.1
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40C to +85C) but are tested at +25C
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7. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5V, Tamb = +25C No. 13 Parameters IF Gain 12 dB 14 dB 16 dB 18 dB 20 dB 22 dB 24 dB 13.1 IF gain (programmable with bit 6 - bit 9) 26 dB 28 dB 30 dB 32 dB 34 dB 36 dB 38 dB 40 dB 42 dB 14 14.1 14.2 14.3 15 15.1 15.2 15.3 16 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 Note: SWO1 (Open Drain) Output voltage LOW Output leakage current HIGH Maximum output voltage SW2/AGC (Open Drain in Switch Mode) Output voltage LOW Output leakage current HIGH Maximum output voltage 3-wire Bus, ENABLE, DATA, CLOCK Input voltage Clock frequency Period of CLK Rise time EN, DATA, CLK Fall time EN, DATA, CLK Set-up time Hold time EN Hold time DATA High Low 23-25 24 24 23-25 23-25 23-25 23 25 tH tL tR tF tS tHEN tHDA 100 250 0 250 250 400 100 VBUS VBUS 2.7 -0.3 5.3 +0.8 1.0 V V MHz ns ns ns ns ns ns ns A A B C C C C C C C I = 1 mA, V11 = 6 V 11 11 11 VSWOL IOHL 6 100 160 200 10 mV A V A A C I = 1 mA, VSWO1 = 8.5V 13 13 13 VSWOL IOHL 8.5 100 160 200 10 mV A V A A C 9 12 14 17 17 19 21 23 25 27 29 31 33 35 37 39 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB A(1) A(1) A(1) C(1) A(1) C(1) C(1) C(1) A(1) C(1) C(1) C(1) C(1) C(1) C(1) A(1) Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Minimum and maximum limits are characterized for entire temperature range (-40C to +85C) but are tested at +25C
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8. 3-wire Bus Description
The register settings of the T4260 are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits is transmitted sequentially during each command. One command is used to program all bits of one register. The different registers available (see chapter "3-wire Bus Data Transfer" on page 12) are addressed by the length of the command (number of transmitted bits) and by two address bits that are unique to each register of a given length. 8-bit registers are programmed by 8-bit commands, 16-bit registers are programmed by 16-bit commands and 24-bit registers are programmed by 24-bit commands. Each bus command starts with a falling edge on the enable line (EN) and ends with a rising edge on EN. EN has to be kept LOW during the bus command. The sequence of transmitted bits during one command starts with the MSB of the first byte and ends with the LSB of the last byte of the register addressed. To transmit one bit (0/1), DATA has to be set to the appropriate value (LOW/HIGH) and a LOW-to-HIGH transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is evaluated at the rising edges of CLK. The number of LOW-to-HIGH transitions on CLK during the LOW period of EN is used to determine the length of the command. Figure 8-1. 3-wire Pulse Diagram
8-bit command
EN DATA CLK MSB BYTE 1 LSB
16-bit command
EN DATA CLK MSB BYTE 1 LSB MSB BYTE 2 LSB
24-bit command
EN DATA CLK MSB BYTE 1 LSB MSB BYTE 2 LSB MSB BYTE 3 LSB
e.g. R-divider
27 26 25 24 23 22 21 20 X X 213 212 211 210 29 28 1 0 Addr.
PDFM PDAM Fract.
23
22
21
20
R-Divider
VCO-Divider
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Figure 8-2. 3-wire Bus Timing Diagram
tF tR VHigh tS tR Data tHDA tS tR Clock tF VHigh VLow tH tL tF VHigh VLow tHEN VLow
Enable
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9. 3-wire Bus Data Transfer
Table 9-1.
A24_10 MSB BYTE 1 R-Divider 27 131 26 130 25 129 24 128 23 127 22 126 21 125 20 124 x 139 x 138 213 137 LSB MSB BYTE 2 R-Divider 212 136 211 135 210 134 29 133 28 132 LSB MSB ADDR. 1 x 0 x BYTE 3 PDAM/ FractioPDFM nal 1/0 145 0/1 144 23 Divider VCO 22 21 20 LSB
Control Registers
143 142 141 140
A24_01 MSB 27 109 26 108 25 107 BYTE 1 N2-Divider 24 106 23 105 22 104 21 103 20 102 215 117 214 116 213 115 LSB MSB BYTE 2 N2-Divider 212 114 211 113 210 112 29 111 28 110 LSB MSB ADDR. 0 x 1 x x 0(1) 123 BYTE 3 x 0(1) 122 x 0(1) x 0(1) 217 LSB N2-Divider 216
121 120 119 118
Note:
1. Value has to be 0.
A24_00 MSB 27 87 26 86 25 85 BYTE 1 N1-Divider 24 84 23 83 22 82 21 81 20 80 215 95 214 94 213 93 LSB MSB BYTE 2 N1-Divider 212 92 211 91 210 90 29 89 28 88 LSB MSB ADDR. 0 x 0 x x 0(1) 101 BYTE 3 x 0(1) 100 x 0(1) 99 x 0(1) 98 217 97 LSB N1-Divider 216 96
Note:
1. Value has to be 0.
A16_11 MSB 27 73 26 72 25 71 BYTE 1 DAC2-Gain 24 70 23 69 22 68 21 67 20 66 LSB MSB ADDR. 1 x 1 x x 79 x 78 x 77 x 76 x 75 x 74 BYTE 2 LSB
A16_10 MSB BYTE 1 DAC2-Offset x 59 26 58 25 57 24 56 23 55 22 54 21 53 20 52 LSB MSB ADDR. 1 x 0 x SWAMLF 1= standard 65 BYTE 2 Osc.- Low c. High SWBuffer CP c.CP impulse ON/ OFF 64 HI/ LO HI/ LO 63 62 ON/ OFF 61 LSB SWwire ON/ OFF 60
A16_01 MSB BYTE 1 DAC1-Gain 27 45 26 44 25 43 24 42 23 41 22 40 21 39 20 38 LSB MSB ADDR. 0 x 1 x x 51 x 50 x 49 BYTE 2 LSB 1 = SW2 SW2 SW1 0 = AGC 1 = low 1 = low 1/0 48 1/0 47 1/0 46
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A16_00 MSB x 31 26 30 25 29 BYTE 1 DAC1-Offset 24 28 23 27 22 26 21 25 20 24 LSB MSB ADDR. 0 x 0 x x 0 37 BYTE 2 x 0 36 x 0 35 x 0 34 x 0(1) 33 LSB SHIFT 1/0 32
Note:
1. Value has to be 0.
A8_11 MSB ADDR. 1 x 1 x BYTE 1 Delay time high Delay time cur. CP2 high cur. CP1 ON/ OFF 23 HI/LO 22 ON/ OFF 21 HI/ LO 20 x 0(1) 19 LSB HCDEL 1/0 18
Note:
1. Value has to be 0.
A8_10 MSB ADDR. 1 x 0 x 1/0 17 BYTE 1 AM/FM IF-AGC 1/0 16 23 15 22 14 RF-AGC 21 13 20 12 LSB
A8_01 MSB ADDR. 0 x 1 x IF-IN AM/FM 11 BYTE 1 VCO HI/LO 10 23 9 22 8 IF-Gain 21 7 20 6 LSB
A8_00 MSB ADDR. 0 x 0 x N2/N1 1/0 5 BYTE 1 PLL ON/ OFF 1/0 4 PD TE/ PD 0(1) 3 22 2 IF-AGC 21 1 20 0 LSB
Note:
1. Value has to be 0.
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10. Bus Control
10.1 IF-AGC
The IF-AGC controls the level of the IF signal that is passed to the external ceramic filter and the IF input (AM pin 35 or FM pin 36 and pin 34). In AM mode the time constant can be selected by the external capacitors at pin 32 (IFAGCA1) and pin 10 (IFAGCA2) and in FM mode by an external capacitor at pin 31 (IFAGCFM). In AM mode, the double pole (by the capacitors at pin 32 and pin 10) allows a better harmonic distortion by a lower time constant. The IF-AGC threshold can be controlled by setting bits 0 to 2 as given in Table 10-1.
Table 10-1.
IF-AGC Threshold
IF-AGC 109 dBV 111 dBV 113 dBV 115 dBV 117 dBV 118 dBV 119 dBV 121 dBV B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1
The IF-AGC ON/OFF can be controlled by bit 16 as given in Table 10-2.
Table 10-2.
IF-AGC
IF-AGC ON/OFF IF-AGC ON IF-AGC OFF B16 0 1
10.2
PD Test
A special test mode for PD is implemented for final production test only. This mode is activated by setting bit 3 = 1. This mode is not intended to be used by customer application. For normal operation bit 3 has to be set to 0.
Table 10-3.
PD-Test Mode
PD TE/PD B3 0 1
Pin 17 = AMLF output (standard) Pin 17 = PD Test mode
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10.3 N1/N2
The N2/N1 bit controls the active N-divider. Only one of the two N-Divider can be active. The N1-Divider is activated by setting bit 5 = 0, the N2-Divider by setting bit 5 = 1.
Table 10-4.
N-Divider
N2/N1 N1-divider active N2-divider active B5 0 1
10.4
IF Amplifier
The IF gain amplifier can be used in AM and FM mode to compensate the loss of the external ceramic bandfilters. The IF gain can be controlled in 2-dB steps by setting bit 6 to bit 9 as given in Table 10-5.
Table 10-5.
IF Gain
B9 0 0 0 0 0 ... 1 1 B8 0 0 0 0 1 ... 1 1 B7 0 0 1 1 0 ... 1 1 B6 0 1 0 1 0 ... 0 1
IF Gain 12 dB 14 dB 16 dB 18 dB 20 dB ... 40 dB 42 dB
The selection of the IF amplifier input can be controlled by bit 11 as given in Table 10-6.
Table 10-6.
IF-IN Operating Mode
IF-IN AM/FM IF-IN FM IF-IN AM B11 0 1
The AM input (pin 35) has an input impedance of 2.5 k for matching with a crystal filter. The FM input (pin 36) has an input impedance of 330 for matching with a ceramic filter.
10.5
VCO
The VCO HI/LO function is controlled by means of bit 10.
Table 10-7.
VCO Operating Mode
VCO HI/LO VCO high current VCO low current B10 0 1
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10.6
RF-AGC
The AM and FM RF-AGC controls the current into the AM and FM pin diodes (FM pin 3 and AM pin 9) to limit the level at the AM or FM mixer input. If the level at the AM or FM mixer input exceeds the selected threshold, then the current into the AM or FM pin diodes increases. If this step is not sufficient in AM mode, the source drain voltage of the MOSFET (pin 11) can be decreased. In AM mode, the time constants can be selected by the external capacitors at pin 42 (RFAGCA1) and at pin 12 (RFAGCAM2) and in FM mode by an external capacitor at pin 33 (RFAGCFM). In AM mode, the double pole (by the capacitors at pin 42 and pin 12) allows a better harmonic distortion by a higher time constant. The RF-AGC can be controlled in 1-dB steps by setting the bits 12 to 15. The values for FM and AM are controlled by bit 17.
Table 10-8.
88 dBV 89 dBV 90 dBV 91 dBV 92 dBV ... 102 dBV 103 dBV
RF-AGC
RF-AGC FM 91 dBV 92 dBV 93 dBV 94 dBV 95 dBV ... 105 dBV 106 dBV B15 0 0 0 0 0 ... 1 1 B14 0 0 0 0 1 ... 1 1 B13 0 0 1 1 0 ... 1 1 B12 0 1 0 1 0 ... 0 1
RF-AGC AM
10.7
Reception Mode
There are two different operation modes, AM and FM, which are selected by means of bit 17 and bit 145 according to Table 9-1 on page 12 and Table 10-1 on page 14. In AM mode (bit 17 = 1), the AM mixer, the AM RF-AGC, the AM divider (prescaler) and the IF AM amplifier (input at pin 35) are activated. In FM mode (bit 17 = 0), the FM mixer, the FM RF-AGC and the IF FM amplifier (input at pin 36) are activated. In AM or FM reception mode, bit 145 has to be set to the corresponding mode. The buffer amplifier input can be connected to pin 16 (with the external FM loop filter) by bit 145 = 0 and to pin 17 (with the external AM loopfilter) by bit 145 = 1. The AM/FM function for the tuner part is controlled by bit 17 as given in Table 10-9. Table 10-9. Tuner Operating Modes
AM/FM FM AM B17 0 1
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10.8 PLL
The PLL can switch off by bit 4 = 0. In this case, the N-Divider input signal is internally connected to ground.
Table 10-10. PLL Mode
PLL ON/OFF PLL OFF PLL ON B4 0 1
10.9
HCDEL
There are two registers, HCDEL 1 (bits 20 and 21) and HCDEL 2 (bits 22 and 23), to control the delay time of the high-current charge pump and to deactivate them. bit 18 (HCDEL) determines whether register HCDEL 1 or 2 is used.
Table 10-11. High-current Charge Pump Delay Time Register
HCDEL 1/2 Select Mode HCDEL 1 HCDEL 2 HCDEL (B18) 0 1
If bits 20 and 21 (HCDEL 1) or bits 22 and 23 (HDCEL 2) are both set to 0, then the high-current charge pump is deactivated. Otherwise, the delay time can be selected as described in Table 10-12.
Table 10-12. Delay Time of HCDEL Register
High-current Charge Pump OFF Delay time 5 ns Delay time 10 ns Delay time 15 ns B21/B23 0 0 1 1 B20/B22 0 1 0 1
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10.10 2-bit Shift
A divider 2-bit shift (bit 32 = 0) allows faster frequency changes by using a four times higher step frequency (e.g., fPDF = 50 kHz instead of fPDF = 12.5 kHz). If the PLL is locked (after the frequency change), the normal step frequency (e.g., fPDF = 12.5 kHz) will be active again. If no 2-bit shift is used (bit 32 = 1), the frequency changes will be done with the normal step frequency (12.5 kHz). In 2-bit shift mode the N- and R-divider are shifted by two bits to the right (this corresponds by a R- and N-divider division by 4). An important condition for this mode is that the R-divider has to be a multiple of 4.
Table 10-13. Manual and Lock Detect Shift Mode
2-bit Shift Dividers 2-bit shift No shift B32 0 1
10.11 SW1 (Pin 13)
The switching output SW1 (pin 13) is controlled by bit 46 as given in Table 10-14.
Table 10-14. Switching Output
SW1 High Low Note: SW1 is an open-drain output. B46 0 1
Figure 10-1. Internal Components at SW1
SW1
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10.12 SW2/AGC (Pin 11)
The pin SW2/AGC works as a switching output (open drain, pin 11) or as an AM AGC-control pin to control the cascade stage of an external AM-preamplifier. The SW2/AGC is controlled by bits 47 and 48 as given in Table 10-15.
Table 10-15. Switching Output 2/AGC Mode
SW2/AGC AGC function High Low Note: In AGC mode, the output voltage is 6V down to 1V. B48 0 1 1 B47 X 0 1
Figure 10-2. Internal Components at SW2/AGC
VS AGC SWO/AGC SW2
10.13 Test Mode
A special test mode is implemented for final production test only. This mode is activated by setting bit 123 = 1. This mode is not intended to be used by customer application. For normal operation bit 123 has to be set to 0.
Table 10-16. Test Mode
Test Mode ON OFF B123 1 0
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10.14 AM Mixer
The AM mixer is used for up-conversion of the AM reception frequency to the IF frequency. Therefore, an AM prescaler is implemented to generate the necessary LO frequency from the VCO frequency. The VCO divider can be controlled by the bits 140 to 143 as given in Table 10-17. (The VCO divider is only active in AM mode) Table 10-17. Divider Factor of the AM Prescaler
Divider AM Prescaler Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10 B143 0 0 0 0 0 0 0 0 1 B142 0 0 0 0 1 1 1 1 x B141 0 0 1 1 0 0 1 1 x B140 0 1 0 1 0 1 0 1 x
10.15 FM Mixer
In the FM mixer stage, the FM reception frequency is down-converted to the IF frequency. The VCO frequency is used as LO frequency for the mixer.
10.16 PLL Loop Filter
The PLL loop filter selection for AM and FM mode can be controlled by bit 145 as given in Table 10-18.
Table 10-18. Loop Filter Operating Mode
PDAM/PDFM PDFM active PDAM active B145 0 1
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10.17 Fractional Mode
The activated fractional mode (bit 144 = 0) in connection with the direct shift (bit 32 = 0) allows fast frequency changes (with the help of the 2-bit shift) with a four times higher step frequency. After the frequency change, the normal step frequency is active again. If the fractional mode is deactivated (bit 144 = 1) and direct shift mode is active, (bit 32 = 0) the VCO frequency is set to the next lower frequency which is many times the amount frequency of 4 times step frequency. This means that the 2 shifted bits of the active N-Divider are not used in this mode. The shift bits are interpreted as logic 0. The fractional mode with direct shift mode deactivated (bit 32 = 1) allows normal frequency changes with a step frequency of 12.5 kHz.
Table 10-19. Fractional Mode
Fractional ON OFF B144 0 1
10.18 Spurious Suppression
In fractional and direct shift mode the spurious suppression is able by SW wire and SW impulse.
Table 10-20. Spurious Suppression by SW Wire
SW Wire OFF ON B60 0 1
Table 10-21. Spurious Suppression by Correction Current Charge Pump
SW Impulse OFF ON B61 0 1
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10.19 Charge Pump (AMLF/FMLF)
AMLF/FMLF is the current charge pump output of the PLL. The current can be controlled by setting the bits 62 and 63. The loop filter has to be designed correspondingly to the chosen pump current and the internal reference frequency. During the frequency change, the high-current charge pump (bit 62) is active to enable fast frequency changes. After the frequency change, the current will be reduced to guarantee a high S/N ratio. The low-current charge pump (bit 63) is then active. The high current charge pump can also be switched off by setting the bits of the active HCDEL register to 0 (bit 20 and bit 21 [HCDEL 1] or bit 22 and bit 23 [HCDEL 2]). The current of the high-current charge pump is controlled by bit 62 as given in Table 10-22.
Table 10-22. High-current Charge Pump
High-current Charge Pump 1 mA 2 mA B62 0 1
The current of the low-current charge pump is controlled by bit 63 as given in Table 10-23.
Table 10-23. Low-current Charge Pump
Low Current Charge Pump 50 A 100 A B63 0 1
10.20 External Voltage at AMLF (Oscillator)
The oscillator (pin 22) can be switched on/off by bit 65. It is possible to use the oscillator buffer as an input or as an output. At the AMLF (pin 17), an external tuning voltage can be applied (bit 65 = 0). If this is not done, the IC operates in standard mode (bit 65 = 1). The oscillator, oscillator buffer and the AMLF are controlled by the bits 65 and 64 as given in Table 10-24 on page 22.
Table 10-24. Oscillator Operating Modes
Oscillator OFF ON ON Oscillator Buffer INPUT OFF OUTPUT AMLF (Pin 17) INPUT f. DAC's AMLF (standard) AMLF (standard) B65 0 1 1 B64 X 0 1
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10.21 DAC1, 2 (Pins 1, 2)
For automatic tuner alignment, the DAC1 and DAC2 of the IC can be controlled by setting gain and offset values. The principle of the operation is shown in Figure 10-3. The gain is in the range of 0.67 x VTUNE to 2.09 x VTUNE. The offset range is +0.98V to -0.98V. For alignment, DAC1 and DAC2 are connected to the varicaps of the preselection filter and the IF filter. For alignment, offset and gain are set for having the best tuner tracking. Figure 10-3. Block Diagram of DAC1, 2
VTUNE Gain +/DAC1, 2
Offset
The gain of DAC1 and DAC2 has a range of approximately 0.67 x V(TUNE) to 2.09 x V(TUNE). This range is divided into 255 steps. One step is approximately (2.09 - 0.67)/255 = 0.00557 x V(TUNE). The gain of DAC1 can be controlled by the bits 38 to 45 (20 to 27) and the gain of DAC2 can be controlled by the bits 66 to bit 73 (20 to 27) as given in Table 10-25.
Table 10-25. Gain of DAC1, 2
Gain DAC1 Approximately Gain DAC2 Approximately 0.6728 x V(TUNE) 0.6783 x V(TUNE) 0.6838 x V(TUNE) 0.6894 x V(TUNE) ... 0.9959 x V(TUNE) ... 2.0821 x V(TUNE) 2.0877 x V(TUNE) 2.0932 x V(TUNE) Note: B45 B73 0 0 0 0 ... 0 ... 1 1 1 B44 B72 0 0 0 0 ... 0 ... 1 1 1 B43 B71 0 0 0 0 ... 1 ... 1 1 1 B42 B70 0 0 0 0 ... 1 ... 1 1 1 B41 B69 0 0 0 0 ... 1 ... 1 1 1 B40 B68 0 0 0 0 ... 0 ... 1 1 1 B39 B67 0 0 1 1 ... 1 ... 0 1 1 B38 B66 0 1 0 1 ... 0 ... 1 0 1 Decimal Gain Decimal Gain 0 1 2 3 ... 58 ... 253 254 255
Offset = 64 (intermediate position)
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The offset of DAC1 and DAC2 has a range of approximately +0.98 V to -0.99 V. This range is divided into 127 steps. One step is approximately 1.97 V/127 = 15.52 mV. The offset of DAC1 can be controlled by the bits 24 to bit 30 (20 to 26) and the offset gain of DAC2 can be controlled by the bits 52 to bit 58 (20 to 26) as given in Table 10-26.
Table 10-26. Offset of DAC1, 2
Offset DAC1 Approximately Offset DAC2 Approximately 0.9815V 0.9659V 0.9512V 0.9353V ... -0.0120V ... -0.9576V -0.9733V -0.9890V Note: 1 1 1 1 B30 B58 0 0 0 0 B29 B57 0 0 0 0 ... 0 ... 1 1 1 B28 B56 0 0 0 0 ... 0 ... 1 1 1 B26 B55 0 0 0 0 ... 0 ... 1 1 1 B26 B54 0 0 0 0 ... 0 ... 1 1 1 B25 B53 0 0 1 1 ... 0 ... 0 1 1 B24 B52 0 1 0 1 ... 0 ... 1 0 1 Decimal Offset Decimal Offset 0 1 2 3 ... 64 ... 125 126 127
Gain = 58 (intermediate position)
10.22 Permitted DAC Conditions
The internal operation amplifier of the DACs should not operate with a too high internal difference voltage at their inputs. This means that a voltage difference higher than 0.5V at the internal OP input should be avoided in operation mode. The respective output OP in the DAC is necessary for the addition and amplification of the tuning voltage (at pin 18) with the desired voltage gain and offset value. If the tuning voltage reaches a high value e.g. 9V, with a gain setting of 2 times VTUNE and an offset of +1V, then the output OP of the DAC should reach the (calculated) voltage of 19V. The supply voltage of e.g. 10V, however, limits the output voltage (of the DAC) to 10V maximum. Due to the (limiting) supply voltage and the internal gain resistance ratio of 6, the missing 9V (calculated voltage - Vs) cause a voltage of 1.5V at the OP input. This condition may not remain for a longer period of time. As long as the calculated DAC output voltage value does not exceed the supply voltage value by more than 3V, no damages should occur during the product's lifetime as the input voltage of the internal OP input voltage does not exceed 0.5V. VTUNE x DAC gain factor + DAC offset < VS + 3V (9V x 2 + 1V) < 10V + 3V (condition not allowed) This means when having a gain factor of 2 and an offset value of 1V, the tuning voltage should not exceed 6V.
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Maximum tuning voltage < (VS + 3 V - DAC offset)/DAC gain factor e.g.: maximum tuning voltage = (10V + 3V - 1V)/2 = 6V It is also possible to reduce the gain or the offset value instead of (or along with) the tuning voltage. Figure 10-4. Internal Components of DAC1, 2
VS
DAC1, 2
11. Input/Output Interface Circuits
11.1 VTUNE, AMLF and FMLF (Pins 16-18)
VTUNE is the loop amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier. Figure 11-1. Internal Components at VTUNE, AMLF and FMLF
VS VS
V5 VTUNE AMLF/FMLF
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11.2
EN, DATA, CLK (Pins 23-25)
All functions can be controlled via a 3-wire bus consisting of Enable, Data and Clock. The bus is designed for microcontrollers which can operate with 3-V supply voltage. Details of the data transfer protocol can be found in Section 8. "3-wire Bus Description" on page 10. Figure 11-2. Internal Components at Enable, Data and Clock
V5
EN DATA CLK
Figure 11-3. Block Diagram of the PLL Core
14 - BIT
LATCH R - DIV.
SWITCH
BIT 18 BIT 32 HCDEL 1 HCDEL 2
SHIFT 2 BIT
fref
R - DIVIDER
DELAYTIME high cur. CP
B145 AM/FM
AM - LOOP FILTER
PHASE DETECTOR
CHARGE PUMP
AM/FM FILTER
FM - LOOP FILTER
N/N+1 DIVIDER
PREAMP B62,63 B61
VCO
SHIFT 2 BIT
SWITCH N+1, N
MUX N1 N2 2 - BIT (LSB) B5 LATCH N - DIV 1 LATCH N - DIV 2
ACCU 2 - BIT
B60, B144
18 - BIT
18 - BIT
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11.3 PLL Core Block Diagram Description
The two N-dividers are stored in two 18-bit memory register (LATCH N-DIV) and the R-divider in a 14-bit memory register (LATCH R-DIV). One of the two N-dividers (N1 or N2) can be activated by bit 5 as active N-divider (with the 18-bit multiplexer MUX). The (divider) 2-bit shift mode can be activated with bit 32 = 0. The N- and R-divider are shifted two bits to the right in this shift mode. Because the two lowest R-divider bits (bit 124 and bit 125) are 0 they do not have to be evaluated. In opposite to the R-divider the lowest two N-divider bits (bit 102 and bit 103 or bit 80 and bit 81, depends on the active N-divider) are special evaluated in the ACCU block if fractional mode is active (bit 144 = 0). The two lowest N- and R-divider bits are also called shift bits. The SWITCH N+1, N block is steering the division through N or N+1 in the N-divider if fractional and 2-bit shift mode are active. There is only a division by N if the fractional mode is deactivated in 2-bit shift mode. The output signals of the 18-bit N-divider and 14-bit R-divider will be compared in the PHASEDETECTOR which one activates the sink and source currents of the charge pumps (CP). There are also two HCDEL registers (for the high current CP delay time) but only one of them is active. One of the HCDEL registers can be activated by bit 18. The delay time of the HCDEL register can be selected with bit 20 and bit 21 or bit 22 and bit 23). The current for the high CP (HCCP) can be set by bit 62 and the current for the low current CP (LCCP) by bit 63. With bit 145 the AM- or FM-Loopfilter (pin) can be activated. It is also possible to use the AM-Loopfilter in FM mode (instead of the FM-Loopfilter) or the FM-Loopfilter in AM mode.
11.4
High-speed Tuning
The fractional mode (bit 144 = 0) in connection with the direct shift mode (bit 32 = 0) allows very fast frequency changes with four times the step frequency (50 kHz = 4 x fPDF) at low frequency steps (e.g., fPDF = 12.5 kHz). In direct shift mode, the R- and the N-divider are shifted by 2 bits to the right (this corresponds to a R- and N-divider division by 4 or a step frequency multiplication by 4). Due to the 2-bit shift, a faster tuning response time of approximately 1 ms instead of 3-4 ms for a tune over the whole FM band from 87.5 MHz to 108 MHz is possible with fPDF = 12.5 kHz. If the FM receiving frequency is 103.2125 MHz (with e.g. fPDF = 12.5 kHz and fIF = 10.7 MHz), an N-divider of 9113 and an R-divider of 12 are necessary when using a reference-frequency (fref) of 150 kHz. fVCO = fIF + frec = 10.7 MHz + 103.2125 MHz = 113.9125 MHz fPDF = fVCO/N = fref/R = 113.9125 MHz/9113 = 150 kHz/12 = 12.5 kHz An important condition for the use of the fractional mode is an R-divider with an integer value after the division by 4 (R-dividers have to be a multiple of 4). After a 2-bit shift (divider division by 4), the R-divider is now 3 (instead of 12) and the N-divider is 2278.25 (instead of 9113). The new N-divider of 2278.25 is also called 1/4 fractional step because the modulo value of the N-divider is 0.25 = 1/4. In total, there are 4 different fractional 2-bit shift steps: full, 1/4, 1/2 and 3/4 step.
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If the fractional mode is switched off (bit 144 = 1) during direct shift mode (bit 32 = 0), the modulo value of the N-divider will be ignored (the new N-divider is then 2278 instead of 2278.25). This means that the PLL locks on the next lower multiple frequency of 4 x f PDF (in our case fPDF = 12.5 kHz). The new VCO frequency (fVCO) is then 113.9 MHz (instead of 113.9125 MHz in fractional mode). Also the PLL has additionally a special fractional logic which allows a good spurious suppression in the fractional and direct shift mode. Activating the wire switch (bit 60 = 1) and the correction charge pump (bit 60 = 1) the spurious suppression is active.
11.5
Charge Pump Current Settings
Bit 62 (0 = 1 mA; 1 = 2 mA) allows to adjust the high current, which is active during a frequency change (if the delay time of the active HCDEL register is not switched off). A high charge pump current allows faster frequency changes. After a frequency change, the current reduction is reduced (in locked mode) to the low current which is set by bit 63 (0 = 50 A; 1 = 100 A). A lower charge pump current guarantees a higher S/N ratio. The high current charge pump can be switched off by the active HCDEL register bits. In this case, when HCDEL 1 is active and the bits 20 and 21 are 0 (HCDEL 1 delay time = off) or HCDEL 2 is active and the bits 22 and 23 are 0 (HCDEL 2 delay time = off), only the low current charge pump (current) is active in locked and in the frequency change mode.
11.6
AM Prescaler (Divider) Settings
The AM mixer is used for up-conversion of the AM reception frequency to the IF frequency. Therefore, an AM prescaler is implemented to generate the necessary LO from the VCO frequency. For the reception of the AM band, different prescaler (divider) settings are possible. Table 11-1 on page 29 lists the AM prescaler (divider) settings and the reception frequencies. fVCO = 98.2 MHz to 124 MHz fIF = 10.7 MHz frec = fVCO - fIF fVCO = AM prescaler x (frec + fIF) The following formula can also be useful by AM frequencies higher than 20 MHz: fVCO = AM prescaler x (frec - fIF)
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Table 11-1. AM Prescaler (Divider) Settings and the Reception Frequencies
Minimum Reception Frequency [MHz] 87.5 38.4 22.033 13.85 8.94 5.667 3.329 1.575 0.211 0 Maximum Reception Frequency [MHz] 113.3 51.3 30.633 20.3 14.1 9.967 7.014 4.8 3.078 1.7
Divider (AM Prescaler) No divider Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10 Note:
The AM Prescaler Divider Settings with fVCO from 98.2 MHz to 124 MHz is only an example. The tuning range depends on the tuning diode and the inductor in the VCO circuit. The tank of the VCO should be designed for a maximum range at pin 18 (VTUNE) of 1.5 V to VSPLL - 1 V for a good S/N performance.
The N- and R- divider can be calculated as following: N = AM Prescaler x (frec + fIF)/fstep N = (frec + fIF)/fstep R = fref/fstep fVCO = N x fstep fref = reference oscillator frequency (pin 27) Example of AM settings: If the receiving frequency is 0.84 MHz (AM) and the following conditions are: fref = 4 MHz; fstep = 10 kHz; fIF = 10.7 MHz and an AM-Prescaler of 10 a N-Divider of 11540 and a R-Divider of 400 is necessary. R = fref/fstep = 4 MHz/10 KHz = 400 N = AM Prescaler x (frec + fIF)/fstep = 10 x (0.84 MHz + 10.7 MHz)/10 KHz = 11540 (AM mode) (FM mode) (For all modes)
11.7
External Voltage at AMLF (Pin 17)
By using two ICs, for example, it is possible to operate the AMLF (pin 17) of the second IC either with the tuning voltage (VTUNE [pin 18]), the DAC 1 voltage [pin 1] or the DAC 2 voltage [pin 2] from the first T4260. For voltage reduction at the AMLF [pin 17], a voltage factor ratio of 100/16 (R1/R2) is required. This means that an applied voltage from 0.5 V at pin 17 (AMLF) corresponds to a tuning voltage of 3.625V. It is recommended to use R1 with 100 k and R2 with 16 k. The allowed range of R1 is 10 k to 1 M and 1.6 k to 160 k for R2.
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Figure 11-4. External Voltage at AMLF (Pin 17)
T4260Gain VTUNE or DAC
R1
R2
AMLF T4260
The maximum input voltage at the AMLF input (pin 17) depends on the applied supply voltage as well as on the gain and offset settings. To avoid any damages during the product's lifetime, the following formulas regarding SWAMLF voltage, gain and offset settings have to be observed (see Section 10.22 "Permitted DAC Conditions" on page 24). VSWAMLF x ([R1 + R2]/R2) x DAC gain factor + DAC offset < VS + 3V (R1 + R2)/R2 = 7.25 This means when having a gain factor of 2 and an offset value of 1V, the applied SWAMLF voltage should be limited to a voltage lower than 0.83V. SWAMLF voltage < (VS + 3V - DAC offset)/(DAC gain factor x 7.25) e.g.: maximum SWAMLF voltage = (10V + 3V - 1V)/(2 x 7.25) = 0.83V It is also possible to reduce the gain or offset instead (or along with) the SWAMLF voltage.
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Figure 11-5. Test Circuit
Test Point
1 DAC1 10n 2 DAC2 10n 3 FMAGCO 4 MXFMIA 10n 3k 5 MXFMIB 6 GNDRF 7 MXAMIB 10n 8 MXAMIA 9 AMAGCO 10 IFAGCA2 11 SW2/AGC
MXFMOB 44 330 MXFMOA 43 RFAGCA1 42 VST 41 MXAMOA 40 MXAMOB 39 GNDT 38 VRT 37 100n IFINFM 36 330 IFINAM 35 2k4 IFREF 34 100n 100k VST 100n
12 RFAGCA2 RFAGCFM 33 13 SW1 14 VRVCO 100n IFAGCA1 32 100k IFAGCFM 31 IFOUTA 30 100 16 FMLF 100n 1n 5k1 17 AMLF 18 VTUNE 10k 5k6 19 OSCGND 1n 22p 20 OSCE 47p 21 OSCB 22 OSCBUF DATA 25 CLK 24 EN 23 VRPLL 26 10n GNDPLL 28 REFFREQ 27 IFOUTB 29 10n
VSPLL
15 VSPLL
15p
BUS
10n
10n
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4528M-AUDR-03/08
Figure 11-6. Application Circuit
P2 GNDT R2 180 R5 2R7 C1 10 C2 100n F2 C3 100p 44 43
MXFMOB MXFMOA
P3 GNDPLL C13 10 IFoutA Bu2 IFoutB Bu3 C15 REFFREQ Bu4 DATA P4 CLK P5 EN P6
EN
C4 1 R3 300
C7 100n
R8 2k2
KF2
VS_T R1 P1 2R7
KF1 F1 R6 300 C9 100n C5 C6 C8 C10 C11 C12 100n220n100n 34 33 32
IFAGCA1 RFAGCA2 RFAGCFM IFREF
C14 100n
100n
220n 100n 47p 42 41 40 39 38 37 36 35
MXAMOA MXAMOB RFAGCA1 IFINAM IFINFM VST GNDT VRT
31 30 29 28 27 26
IFOUTA IFOUTB REFFREQ GNDPLL IFAGCFM VRPLL
25 24 23
DATA CLK OSCB
SW2/AGC
AMAGCO
FMAGCO
OSCGND
IFAGCA2
10 11 12 13 14 15 16 17 18 19 20 21 22 OSCBUF C47 C48 C28 C37 C39 Bu5 P11 P12 P13 C16 10n 47 22 100n 100n 100n DAC2 FM AM VT 22p 47p C31 C50 OSCB C41 C40 P8 P15 12p Bu4 C17 10n L2 100n C 15n SW1 42 1n C49 100H C23 C24 BC 848 R14 1n C32 6p8 T3 R24 C43 R R11 6p8 F5 68k 25 1n 6p8 CD1 6k2 F3 L3 C25 R16 2n2 5k1 C38 C22 4n7 2m2 2k7 68k 100n R26 18p 100 C46 CD3 BB804 T4 BB804 C44 R12 R9 1n J109 100n R27 470 68k R10 C45 C21 5k6 10 C20 10n 10p C R17 27p L1 19 C34 R23 47 F4 27 C18 22 T1 220n BFR93A 10n VS_PLL BB804 P10 R13 R18 T2 1k P16 CD2 BC848B 470k R19 D1 C26 C27 470k R15 3p9 S391D 10n 1k DAC1 P7 C36 10n C35 10p AMPREIN P14 P9 AMAGCO R28 3k9 R22 470k
1
2
3
4
5
6 7 C29
8 9 C30
Bu1 Ant
L4 47
D2
S391D C33
D3 100n S391D
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OSCBUF
MXAMIB
MXAMIA
MXFMIA
MXFMIB
GNDRF
VRVCO
VTUNE
VSPLL
OSCE
AMLF
DAC1
DAC2
FMLF
SW1
T4260
12. Ordering Information
Extended Type Number T4260-ILSH T4260-ILQH Package Pb-free SSO44 Pb-free SSO44 Remarks Tube Taped and reeled
13. Package Information
Package SSO44
Dimensions in mm
18.05 17.80 9.15 8.65 7.50 7.30
2.35 0.3 0.8 16.8 44 23 0.25 0.10
0.25 10.50 10.20
technical drawings according to DIN specifications
1
22
14. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4528M-AUDR-03/08 4528L-AUDR-05/07 History * Figure 11-6 "Application Circuit" on page 32 changed * Put datasheet in a new template * Number 6.4 in section 7 "Electrical Characteristics" on page 6 added * Put datasheet in a new template * Pb-free logo on page 1 deleted * Table 10-8 "RF-AGC" on page 17 changed
4528K-AUDR-03/07
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